21Mar How is Microprocessor Manufactured?-Part 3

Some of the masks are used to add the metallization layers, which are the metal interconnects used to tie all the individual transistors and other components together. Most older chips use aluminum interconnects, although during 2002 many moved to copper. The first commercial PC processor chip to use copper was the 0.18-micron Athlon made in AMD’s Dresden fab, and Intel shifted the Pentium 4 to copper with the 0.13-micron Northwood version. Copper is a better conductor than aluminum and allows smaller interconnects with less resistance, meaning smaller and faster chips can be made. The reason copper hadn’t been used until recently is that there were difficult corrosion problems to overcome during the manufacturing process that were not as much of a problem with aluminum. Now that these problems have been solved, more and more chips are fabricated with copper interconnects.

Another technology that is becoming common is the use of silicon on insulator (SOI) instead of CMOS technology. AMD uses SOI for its 90-namometer (0.09-micron) processors, and it’s expected that SOI, which provides better insulation than CMOS for transistors, will continue to grow in popularity. A completed circular wafer has as many chips imprinted on it as can possibly fit. Because each chip usually is square or rectangular, there are some unused portions at the edges of the wafer, but every attempt is made to use every square millimeter of surface.

The industry is going through several transitions in chip manufacturing. The trend in the industry is to use both larger wafers and a smaller chip die process. Process refers to the size and spacing of the individual circuits and transistors on the chip. In late 2001 and into 2002, chip manufacturing processes began moving from the 0.18-micron to the 0.13-micron process, the metal interconnects on the die began moving from aluminum to copper, and wafers began moving from 200mm (8″) to 300mm (12″) in diameter. The larger 300mm wafers alone enable more than double the number of chips to be made, compared to the 200mm used previously. The smaller 0.13-micron and 0.09-micron (90-nanometer) processes enables more transistors to be incorporated into the die while maintaining a reasonable die size and allowing for a sufficient yield. This means the trend for incorporating more and more cache within the die will continue, and transistor counts will rise to 1 billion per chip or more by 2010.

As an example of how this can affect a particular chip, let’s look at the original Pentium 4. The standard wafer size used in the industry for many years was 200mm in diameter, or just under 8″. This results in a wafer of about 31,416 square millimeters in area. The first version of the Pentium 4 with the Willamette core used a 0.18-micron process with aluminum interconnects on a die that was 217 square millimeters in area, had 42 million transistors, and was made on 200mm wafers. Therefore, up to 145 of these chips could fit on a 200mm (8″) wafer.